An imager, for example, a CMOS imager includes a focal plane array of pixels; each pixel includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel also typically has a floating diffusion region, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. Imagers incorporating global storage include a transistor for transferring charge from the photosensor to a storage node, and a transistor for transferring charge from the storage node to the floating diffusion region (unless the floating diffusion region is also serving as the storage region). The imager also includes a transistor to reset the floating diffusion region. The imager may include a transistor to reset the photodiode.
FIG. 1 is an illustration of a conventional four transistor (4T) pixel 100 typically used in a CMOS imager. The pixel 100 includes a photosensor 105, shown as a photodiode, a floating diffusion charge storage region (floating diffusion region) 110, and four transistors: a transfer transistor 115, a reset transistor 120, a source follower transistor 125, and a row select transistor 130. The pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 115, a RST control signal for controlling the conductivity of the reset transistor 120, and a ROW control signal for controlling the conductivity of the row select transistor 130. The charge stored at the floating diffusion region 110 controls the conductivity of the source follower transistor 125. The output of the source follow transistor 125 is presented at node 135, which is connected to a column line of a pixel array, when the row select transistor 130 is conducting.
The states of the transfer and reset transistors 115, 120 determine whether the floating diffusion region 110 is coupled to the light sensitive element 105 for receiving photo-generated charge accumulated by the light sensitive element 105 during a charge integration period, or a source of pixel power VAAPIX from node 140 during a reset period.
The pixel 100 is operated as follows. The ROW control signal is asserted to cause the row select transistor 130 to conduct. At the same time, the RST control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion region 110 to the pixel power potential VAAPIX at node 140, and resets the voltage at this floating diffusion region 110 to the pixel power potential VAAPIX, less a voltage drop associated with reset transistor 120. This voltage drop can be avoided by boosting the reset signal. The pixel 100 outputs a reset signal (Vrst) at node 135. As will be explained in greater detail below in connection with FIG. 2, node 135 is typically coupled to a column line 235 (FIG. 2) of an imager 200, which supplies a constant current through the source follower transistor 125.
While the transfer transistor 115 is off, the photosensor 105 is exposed to incident light and accumulates charge based on the level of the incident light during a charge integration period. After the charge integration period and after the RST control signal turns off reset transistor 120, the TX control signal is asserted. This couples the floating diffusion region 110 to the photosensor 105. Charge flows through the transfer transistor 115 and diminishes the voltage at the floating diffusion region 110 in accordance with the accumulated charge and the capacitance of the floating diffusion node. The pixel 100 thus outputs a photo signal (Vsig) at node 135.
FIG. 2 is an illustration of an imager 200 that includes a plurality of pixels 100 forming a pixel array 205. Due to space limitations the pixel array 205 is drawn as a 4 row by 4 column array in FIG. 2. One skilled in the art would recognize that most imagers 200 would ordinarily include many more pixels 100 in the array. The imager 200 also includes row circuitry 210, column circuitry 215, a digital processing circuit 220, and a storage device 225. The imager 200 also includes a controller 230, for controlling operations of the imager 200.
The row circuitry 210 selects a row of pixels 100 from the pixel array 205. The pixels 100 in the selected row output their reset and pixel signals Vrst, Vsig to the column circuitry 215, via column output lines 235, which samples and holds the reset and pixel signals Vrst, Vsig for each pixel in a row. The rows are activated one by one in sequence to send successive row signals to column output lines 235.
The column circuitry 215 is responsible for converting the pixel reset Vrst and photo Vsig signals into digital values that can then be further processed in the digital domain. In order to do this, the column circuitry 215 samples and holds the reset Vrst and photo Vsig signals produced by each pixel. An analog pixel output signal (Vpixel) is formed as the difference between the reset Vrst and photo Vsig signals, i.e., Vpixel=Vrst−Vsig. The pixel output signal Vpixel is then converted into a digital value. Imager 200 uses a column parallel architecture, in which the outputs of several pixels 100 in the selected row are simultaneously sampled and held, and converted to digital values. The digital values are output to the digital processing circuit 220, which performs image processing on the digital values to produce a digital image. The processed digital values are stored in the storage device 225. The controller 230 is coupled to the pixel array 205, row circuitry 210, column circuitry 215, and storage device 225, and provides control signals to perform the above described processing.
One way of providing a global shutter function is the addition of a storage gate transistor between the photosensor 105 and transfer gate 115. Such a structure is illustrated in FIG. 3, which illustrates a storage gate transistor 305 and associated storage node SN 315 provided in series between the photosensor 310 and transfer transistor 325. As one of ordinary skill in the art would appreciate, the storage node SN is not necessary in all global shutter devices. The “FD Global Shutter” stores the image on the floating diffusion transistor at the expense of correlated double sampling. As illustrated below, the invention described here also works with “FD Global Shutter” pixels. One of ordinary skill in the art would appreciate that the current invention is applicable to other types of global storage including storage node pixel and shutter pixel.
Typically, one problem encountered when storage nodes are used with, for example, imagers including global storage, is the presence of an increased amount of dark current. This may be caused by surface generation of the dark current or dark current resulting from process induced damage. The dark current of the storage node of global storage pixels may be as much as twenty times greater than the dark current experienced in a pinned photodiode used as a pixel photosensor. A second problem encountered with global storage pixels is leakage charge (or smear charge) which is the combination of optical and electrical crosstalk to the storage node resulting in a low shutter efficiency (SE). Once the charge stored in the storage node is readout during the readout phase, dark current and smear charge begin to re-accumulate in the storage node prior to the occurrence of the next readout phase. The presence of dark current and leakage charge significantly degrades the image quality. The image quality is especially degraded in low light conditions when the frame rate is reduced to accommodate a longer integration time.